1. Field of the Invention
The present invention generally relates to analog-to-digital converters and it particularly relates to an analog-to-digital converter of a pipeline type and the like in which analog signals are converted to digital signals a plurality of times.
2. Description of the Related Art
In response to the development of the digital signal processing technologies, there is a growing demand of analog-to-digital converter with high resolution and high speed. As an analog-to-digital converter like this (hereinafter referred to as “A-D converter”), an analog-to-digital converter of a pipeline type has been proposed. For example, an A-D converter of a pipeline type having the structure of four stages is laid open in FIG. 4 of Reference (1) in the following Related Art List. In this Reference (1), 4 bits, 3 bits, 3 bits and 3 bits are outputted and thus the total of 10 bits are outputted as digital values at the respective A-D converter blocks.
Related Art List
(1) Japanese Patent Application Laid-Open No. Hei09-275342.
In FIG. 13 of the above Reference (1), a description was given of the A/D converter 42 of a flash type that includes a plurality of voltage comparator circuits 7.3 to 7.13. Also, in FIG. 14 of the above Reference (1), a description was given of the potential comparator 55 and the capacitors 51 to 54 connected to the input terminal thereof, as a structural component of the voltage comparator circuit 7.3.
In such a switched-capacitor type comparator as above, the voltage to store the electric charge in the capacitance needs to be switched by a switch. With this configuration, when the switch is switched, the input analog signal to the sample/hold circuit provided in parallel with the A/D converter changes due to the effect of the electric charge stored in the above capacitance, so that the settling time is longer and therefore the settling speed is slower. In FIG. 2 of the above Reference (1), there is a description of the circuit configuration in which the sample/hold circuit 14 is provided in parallel to the A/D converter 12.